Inside the IBM Heron 156-qubit processor: what makes a real quantum chip work

Every hardware run on Quantum Gap AI lands on one of two IBM Heron processors: ibm_fez or ibm_kingston. They're 156-qubit superconducting devices, currently among the most capable quantum processors available for general access. This piece is a non-PhD tour of how those chips actually work — what's in them, what the daily calibration numbers mean, and which architectural decisions ended up mattering most.

The qubit itself

A Heron qubit is a transmon: a tiny anharmonic oscillator built from a Josephson junction (two superconductors separated by a thin insulator) in parallel with a capacitor. When you cool the chip to ~15 millikelvin — colder than deep space — that junction develops two distinct quantum states you can address as |0⟩ and |1⟩. The "anharmonic" part means the energy gap between |0⟩ and |1⟩ is different from the gap between |1⟩ and |2⟩; that's what lets you drive transitions between the first two without accidentally leaking into the third.

On Heron, transmon frequencies sit around 4-5 GHz. Operations happen via microwave pulses tuned to that frequency. A pulse of the right shape + duration + phase rotates the qubit on the Bloch sphere by a known angle. That's a gate.

The big architectural choice: tunable couplers

The single most important Heron design decision over its predecessors (Eagle, Falcon) is tunable couplers between qubits. Older IBM chips used fixed couplers — always-on couplings that meant every two-qubit gate had to fight crosstalk from neighbours. Heron puts a tunable element between each qubit pair that can be biased "on" (gates fire) or "off" (qubits isolated). The result is dramatically lower crosstalk and significantly better two-qubit gate fidelity.

The two-qubit gate primitive on Heron is the echoed cross-resonance (ECR) gate. It's a Clifford gate equivalent to a CNOT plus single-qubit rotations. Typical ECR fidelity on a calibrated Heron: 99.5%+. Echo away enough environmental noise during the gate and you get the percentage points back that the older chips were leaving on the floor.

Coherence times

The two numbers that bound everything else:

• T1 (energy relaxation) — how long before |1⟩ decays to |0⟩. Typically 150 μs on Heron, varies per qubit per day.
• T2 (dephasing) — how long the qubit retains phase information. Typically 100 μs.

Each gate takes 24-68 nanoseconds (single-qubit) to a few hundred nanoseconds (two-qubit). So a circuit with 200 gates total is fine; a circuit with 2000 sequential gates is on the edge. This isn't a soft limit — it's the hardware's actual physics.

The calibration cadence

A Heron chip is recalibrated daily. Every morning a set of internal benchmarks (RB, Mirror, IPE, single- and two-qubit fidelities, readout fidelity, T1/T2) is run on every qubit pair and the gate pulse parameters are re-tuned. The properties API IBM publishes is current to the most recent calibration.

What this means in practice for the platform: when you run a job, the backend's current calibration is captured into your audit report. If a qubit pair's two-qubit fidelity dropped 0.5% between yesterday and today, your circuit that depends on it will have a slightly noisier output, and the audit captures the exact calibration numbers from the moment your job ran. Every claim is falsifiable against IBM's own published data.

Why 156 qubits and not 433 or 1000?

IBM's Condor (1121 qubits) and Osprey (433) exist. Heron at 156 is the chip you actually get useful work done on. The reason: the more qubits you wire together at fixed connectivity, the more crosstalk you introduce, the harder calibration becomes. Heron's 156 qubits with tunable couplers gets you >99% mean gate fidelity across the chip; the bigger-but-lower-fidelity chips don't beat Heron on any benchmark that involves running an actual algorithm. Useful qubits, not headline qubits.

What the simulator can't tell you

State-vector simulators model perfect qubits — no T1, no T2, no readout error, no crosstalk. They're correct for circuits up to about 30 qubits (which is the rough memory limit) and they're great for checking that your circuit's logic is right. They tell you nothing about whether the circuit will work on real hardware at scale. We wrote a whole post on this: simulator vs IBM hardware.

Try it

Every hardware tool on Quantum Gap AI targets ibm_fez by default. Run the Bell pair tool, ask for cross-backend comparison, and you'll get the same circuit executed on both ibm_fez and ibm_kingston with both calibration snapshots embedded. That's the cleanest way to see the device-specific noise pattern of a real 156-qubit Heron in action.